Linus Torvalds has come out strong against proposed support for RISC-V big endian capabilities within the Linux kernel.
In response to a mailing list comment whether RISC-V big endian “BE” patches being worked on would be able to make it for this current Linux kernel cycle. Linus Torvalds initially wrote:
"Oh Christ. Is somebody seriously working on BE support in 2025?
WHY?
Seriously, that sounds like just stupid. Is there some actual real reason for this, or is it more of the “RISC-V is used in academic design classes and so people just want to do endianness for academic reasons”?
Because I’d be more than happy to just draw a line in the sand and say “New endianness problems are somebody ELSES problem”, and tell people to stop being silly.
Let’s not complicate things for no good reason. And there is NO reason to add new endianness.
RISC-V is enough of a mess with the millions of silly configuration issues already. Don’t make it even worse.
Tell people to just talk to their therapists instead. That’s much more productive."
If you have a file containing 4 bytes, where the first byte in the file is
0x01, second is0x02, third is0x03, and 4th is0x04, and you keep that same order when you load them into the first 4 bytes of memory on an LE machine vs a BE machine, what value does the uint32 located at address 0 contain? On LE it’s0x04030201, on BE it’s0x01020304. So yes, it absolutely matters.Not on RISC-V. The registers don’t really have an endianness. They’re just bit vectors - you can’t address within them.
When you access memory the current endianness setting determines the mapping between the register value and the bytes in memory. It’s the access that has endianness; not the register.